Conventionally, a semiconductor storage device such as an MRAM (Magnetic Random Access Memory) includes a common data bus provided to be common to a plurality of memory units and continuously transfer data via the common data bus (an interleaving operation). In this case, the timing of transfer needs to be controlled in such a manner that the memory units sharing the data bus do not transfer data in an overlapped manner, or data is not transferred to the memory units in an overlapped manner.
Conventionally, in order to control a data transfer timing for each of memory units, a delay circuit needs to be provided so as to correspond to each of the memory units. However, according to such a delay circuit, a delay time varies according to process variations. Such variations in the delay time may cause data to be transferred in an overlapped manner in a data bus.